package mips.instructions;

/**
 * <code>AND</code> instruction<br/>
 * And<br/>
 * @author jnmartin84@gmail.com
 */
public class AND extends Instruction {

	private static final AND INSTANCE = new AND();
	private static final String INSTRUCTION_NAME = "AND";

	private AND(){}

	public static final AND getInstance() {
		return INSTANCE;
	}

	/**
	 * <b>Format:</b><br/>
	 * AND rd, rs, rt<br/><br/>
	 * <b>Description:</b><br/>
	 * The contents of general register rs are combined with the contents of<br/>
	 * general register rt in a bit-wise logical AND operation. The result is placed<br/>
	 * into general register rd.<br/><br/>
	 * <b>Operation:</b><br/> 
	 * T: GPR[rd] &larr; GPR[rs] and GPR[rt]
	 */
	@Override
	public final void execute(final int instruction) {

		mips.instructions.Instruction.RS = (instruction >> 21) & 0x0000001F;
		mips.instructions.Instruction.RT = (instruction >> 16) & 0x0000001F;
		mips.instructions.Instruction.RD = (instruction >> 11) & 0x0000001F;

		mips.R4300i.GPR[mips.instructions.Instruction.RD] = mips.R4300i.GPR[mips.instructions.Instruction.RS] & mips.R4300i.GPR[mips.instructions.Instruction.RT];

		mips.R4300i.PC = mips.R4300i.nPC;
		mips.R4300i.nPC = mips.R4300i.PC + 4;
	}

	/**
	 * {@inheritDoc}
	 */
	@Override
	public final String emit(final int instruction) {

		mips.instructions.Instruction.RS = (instruction >> 21) & 0x0000001F;
		mips.instructions.Instruction.RT = (instruction >> 16) & 0x0000001F;
		mips.instructions.Instruction.RD = (instruction >> 11) & 0x0000001F;


		return 	"		mips.CPU.GPR["+mips.instructions.Instruction.RD+"] = mips.CPU.GPR["+mips.instructions.Instruction.RS+"] & mips.CPU.GPR["+mips.instructions.Instruction.RT+"];\n" + 
				"		\n" + 
				"		mips.CPU.PC = mips.CPU.nPC;\n" + 
				"		mips.CPU.nPC = mips.CPU.PC + 4;\n";
	}

	/**
	 * {@inheritDoc}
	 */
	@Override
	public final String getName(final int instruction) {
		return getName();
	}
	
	/**
	 * {@inheritDoc}
	 */
	@Override
	public final String getName() {
		return INSTRUCTION_NAME;
	}
}